1. Field of the Invention
The present invention relates to a semiconductor device comprising an internal clock generating circuit for receiving an external clock and generating an internal clock, and more in particular to a semiconductor device comprising an internal clock generating circuit for generating a first internal clock (CLK1) in phase with an external clock and a second internal clock 180xc2x0 out of phase (shifted by one-half of a phase) from the external clock.
2. Description of the Related Art
In a system comprising a combination of a plurality of semiconductor devices, it is a common practice to synchronize the operations of the various parts with a clock. For this reason, semiconductor devices other than the one which generates and outputs an original clock include an internal clock generating circuit which receives the clock output from other semiconductor devices and generates an internal clock used for the internal parts thereof. A description herein will be made of a synchronized dynamic random access memory (SDRAM) as an example which performs signal input and output operations with external sources and an internal operation in synchronism with a clock. The present invention, however, is not limited to the SDRAM.
In recent years, a demand has increased for an improved data transfer rate of the SDRAM, and the clock frequency has greatly increased. With an increased clock frequency, however, the problem of the signal deterioration, etc. is posed. As described above, the data signal changes in accordance with the period of the clock, and the frequency of the data signal is one half that of the clock. In view of this, a DDR (double data rate) technique has been proposed, in which the data signal is set to the same frequency as the clock and is retrieved in synchronism with both the leading and trailing edges of the clock.
In the DDR technique, the ideal phase difference between the leading and trailing edges of a clock CLK is 180xc2x0. The external clock actually retrieved, however, often has a phase difference other than 180xc2x0 between the leading and trailing edges due to the load of the signal line, etc. Also, the characteristics of the internal clock generating circuit frequently causes the internal clock to have a phase difference other than 180xc2x0 between the leading and trailing edges thereof. The resulting problem is that if a data signal is retrieved or the internal circuit is operated in synchronism with the leading and trailing edges of the internal clock, the time margin for normal operation cannot be satisfied.
In employing the DDR technique, one solution to the above-mentioned problem would be for the transmitting end of the signal to output a first clock CLK and a second clock /CLK 180xc2x0 out of phase in complementary relation with each other and for the receiving end of the signal to retrieve the signal in synchronism with the leading edges of CLK and /CLK. Another solution to the problem would be to generate a second internal clock exactly 180xc2x0 out of phase with the external clock CLK in the SDRAM using the delay locked loop (DLL) or the like technique from the external clock CLK.
A SDRAM could thus be fabricated incorporating one of the two types of internal clock generating circuits (clock input circuits) depending on the technique used for the system on which it is mounted. In other words, two types of SDRAM could be fabricated, one exclusively using a complementary clock, and the other for exclusively generating a 180xc2x0 clock internally.
Nevertheless, analogous semiconductors having two different specifications would be fabricated at a higher cost due to a lower production efficiency and an inefficient inventory control. The manufacturer which produced a system using such a device would also suffer from an increased cost due to an increased stockpile. Thus, a device is desirable which can be used for both a system using a complementary clock and a system which generates a 180xc2x0 phase clock internally.
Also, with the increase in frequency, the delay of the internal clock of the semiconductor device increases to a significant extent. For example, the layout of a semiconductor sometimes makes it necessary to arrange a data input circuit and a data output circuit at a distance from an internal clock generation circuit. In such a case, the internal clock supplied from the internal clock generation circuit to the data input circuit or the data output circuit is delayed, which causes a deviation of the data input or output operation. Also, some delay is unavoidable in the clock input buffer and the internal clock generation circuit. As long as the clock frequency is not high, such a delay poses no substantial problem. With the increase in clock frequency to 100 MHz or more, however, the situation is aggravated to a significant extent. In order to solve this problem, the present applicant proposes, in U.S. Copending applications Ser. Nos. 08/892,790 and 08/924,705, a method for completely synchronizing the internal clock supplied to the data input circuit and the data output circuit with an external clock using a variable delay line having the delay amount thereof changeable. These applications do not disclose a semiconductor device operating according to a DDR (double data rate) scheme which uses a complementary clock. It has been desired also in a DDR semiconductor that the data input/output operation can be performed totally in synchronism with an external clock.
The present invention is intended to solve this problem, the first object thereof is to provide a semiconductor device usable for both a DDR type system using a complementary clock and a system generating a 180xc2x0 phase internally at the same time, and the second object thereof is to provide a DDR type semiconductor device of which data input/output operations are perfectly synchronized with an external clock.
According to the present invention, there is provided a semiconductor device comprising means for generating a first internal clock and a second internal clock complementary with each other from an external clock, a first clock input circuit (buffer) supplied with a first external clock for producing a first internal clock, a second clock input circuit (buffer) supplied with a second external clock complementary with the first external clock for producing a second clock, a xc2xd phase clock generating circuit for generating a xc2xd phase shift signal having a phase 180xc2x0 different from the first internal clock, a second external clock state detection circuit for judging whether the second external clock is input to the second clock input buffer, and a switch for producing the second clock as a second internal clock in the presence of an input of the second external clock and for producing the xc2xd phase shift signal as a second internal clock in the absence of an input of the second external clock in accordance with the result of judgement at the second external clock state detection circuit.
In the semiconductor device according to this invention, the signal generated from the second external clock is produced as a second internal clock when the second external clock is input thereto, and a xc2xd phase shift signal 180xc2x0 out of phase with the first internal clock is produced as a second internal clock when the second external clock is not input thereto. The semiconductor device according to this invention, therefore, can meet the requirements of the two types of the system at the same time.
When the xc2xd phase shift signal is output as the second internal clock in the absence of the second external clock applied thereto, the second clock input circuit need not be operated. The second clock input circuit, therefore, is desirably turned off to save power in such a case.
Also, as long as the second external clock is input, the xc2xd phase clock generating circuit need not to be operated. Therefore, the xc2xd phase clock generating circuit is desirably turned off to save power. In such a case, the xc2xd phase clock generating circuit, if the first internal clock is not being supplied thereto, is substantially turned off.
The xc2xd phase clock generating circuit is made up of a PLL circuit or a delay locked loop (DLL) having a delay line of which the delay amount is selectable in predetermined units of delay.
Various methods are conceivable for realizing the /CLK state detection circuit. In an example configuration, a switching edge of the second clock is detected, so that upon detection of the switching of the second clock, application of the second external clock is judged. In another possible configuration, the voltage of an input pin supplied with the second external clock is fixed to Vcc or Vss, or upon detection that the input pin is open, the absence of the second external clock input is judged. The frequency of the second clock is so high that the switching edge thereof is difficult to detect. Therefore, the /CLK state detection circuit preferably includes a frequency divider to detect the switching edge of the second clock with a longer period than that of the second external clock.
The /CLK state detection circuit is for detecting whether or not the second external clock is input within a predetermined length of time after power is switched on and for subsequently maintaining the judgement, or normally detects the presence or absence of an input of the second external clock.
In the case where a signal of small amplitude is input as a clock signal, the invention may comprise a signal input state detection circuit including a first inverter, a second inverter and a logical circuit as a /CLK state detection circuit. The first inverter includes a first P-channel transistor and a first N-channel transistor connected in series between a high-voltage terminal and a low-voltage terminal of a power supply, wherein the gates of the first P-channel transistor and the first N-channel transistor are impressed with a small-amplitude signal, and the gate width of the first P-channel transistor is sufficiently larger than the gate width of the first N-channel transistor. The second inverter includes a second P-channel transistor and a second N-channel transistor connected in series to each other between the high-voltage terminal and the low-voltage terminal of the power supply, wherein a small-amplitude signal is applied to the gates of the second P-channel transistor and the second N-channel transistor, and the gate width of the second N-channel transistor is sufficiently larger than the gate width of the second P-channel transistor. The logical circuit produces an active signal indicating that a small-amplitude signal is applied upon detection that the output of the first inverter assumes a logical value approximate to the potential of the high-voltage terminal and that the output of the second inverter assumes a logical value approximate to the potential of the low-voltage terminal.
According to a second aspect of the invention, in order to achieve the above-mentioned object, there is provided a semiconductor device regulated in such a manner that first and second external clocks, which are complementary with each other, are in phase with first and second internal clocks, respectively.
Specifically, a semiconductor device according to the second aspect of the invention, which is supplied with first and second external clocks, which are complementary with each other, from an external source, comprises a first clock input circuit supplied with the first external clock for outputting the first internal clock, a second clock input circuit supplied with the second external clock for outputting the second internal clock, a first 0xc2x0 phase adjusting circuit for adjusting the first internal clock into synchronism with the first external clock, and a second 0xc2x0 phase adjusting circuit for adjusting the second internal clock into synchronism with the second external clock.
In the case where a clock signal having a frequency twice that of the external clocks is required, the semiconductor device further comprises a synthesizer for combining the outputs of the first 0xc2x0 phase adjusting circuit and the second 0xc2x0 phase adjusting circuit and producing an internal clock twice higher in frequency than the first and second external clocks.
The first and second 0xc2x0 phase adjusting circuits each include a variable delay circuit for delaying the internal clocks in variable way, and a phase difference detection circuit for detecting the phase difference between the external clock and the clock signal supplied by the clock output of the variable delay circuit and generating a control signal for controlling the delay amount of the variable delay circuit in such a manner as to secure a phase difference of 0xc2x0.
The phase difference detection circuit can either detect the phase difference using an actual signal in the route for supplying the external clock from the clock input circuit through the variable delay circuit or can comprise a dummy circuit equivalent to the particular route for detecting the phase difference with an equal delay amount. Also, the phase difference can be detected when the route is partly constituted with a dummy circuit.
As long as the first internal clock and the second internal clock are out of phase by one half period (180xc2x0) exactly from each other, the first phase difference detection circuit and the second phase difference detection circuit can be combined into a common circuit.
In similar fashion, in the case where the first internal clock and the second internal clock are out of phase from each other by one half period (180xc2x0) exactly, a 0xc2x0 phase adjusting circuit can be provided in which the internal clock combined from the first and second internal clocks and output from the synthesizer is in phase with the first external clock or the second external clock.
The 0xc2x0 phase adjusting circuit includes a variable delay circuit for delaying the internal clock by a variable amount, and a phase difference detection circuit for detecting the phase difference between the first or second external clock and the clock signal output from the variable delay circuit delayed by an amount equivalent to the distance from the first clock input circuit or the second clock input circuit to the synthesizer and generating a control signal for controlling the delay amount in the variable delay circuit in such a manner as to secure a phase difference of 0xc2x0.
Also in this case, the phase difference detection circuit can either detect the phase difference using an actual signal in the route for supplying the external clock from the clock input circuit through the variable delay circuit or can detect the phase difference by causing an equal delay amount using a dummy circuit equivalent to the route